Interesting side story regarding the OC guys' opinions on performance and matching. I was a chip designer at Intel/IBM/Sun for 14 years, with 10 years focusing solely on microprocessors, and a technical basis exists for saying that die from the center of a wafer would have tighter optical control, which could result in a higher speed bin or greater ability to overclock because timing variations across the die would probably be minimized relative to die on the perimeter of the wafer. Notwithstanding the general principle that die at the center are probably tighter controlled, individual variations among die at the center could easily be a greater factor in performance variation than proximity to the center of the wafer. I had only a little exposure to what manufacturing data was externally knowable, but I would be surprised if the location of a particular die within a wafer was programmed into that die or publicly available from the manufacturer (but I don't know that this is not possible).
Strongly agree, also, that transistors with higher leakage can perform better. In MOS transistors, as the turn-on voltage lowers, leakage rises as the square of the voltage change. Additionally, switching current increases as the square of the voltage change. A higher switching current allows individual nodes to switch quicker because node capacitances discharge quicker.
All of this is probably more than anyone cares about but I've learned so much from this group on system issues (which I had no exposure to before) that I do what I can to pay it back.