Hi,
Is there an optimal number of cores for interconnect within a socket? The older intel Xeons had the ring bus, the newer SPs have mesh, I've not researched the EPYC interconnect. Is there a number of cores for each generation at which the interconnect is balanced, above which there is effectively another layer of heirarcy/non-uniform performance? I know this was the case with the older Xeons where additional rings were added, unsure as to the newer architectures.
(This is a different to the question of optimizing overall performance, costs or licensing)
Thanks!
Is there an optimal number of cores for interconnect within a socket? The older intel Xeons had the ring bus, the newer SPs have mesh, I've not researched the EPYC interconnect. Is there a number of cores for each generation at which the interconnect is balanced, above which there is effectively another layer of heirarcy/non-uniform performance? I know this was the case with the older Xeons where additional rings were added, unsure as to the newer architectures.
(This is a different to the question of optimizing overall performance, costs or licensing)
Thanks!